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Altera_Forum's avatar
Altera_Forum
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12 years ago

What to do about excessive internal FPGA clock skew?

Hello, I'm using the Triple Speed Ethernet core and when I run TimeQuest I get the following timing constraints error. The timing requirements are not met by only a small margin but what g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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With the optimized version I'm down to -0.076 ns Skew.

https://www.alteraforum.com/forum/attachment.php?attachmentid=8234

The path shown in the previous screenshot doesn't exist anymore because I cut the paths between the tx-, rx- and control-port-clocks as recommended by Altera.

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Thanks for you info!