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User1591865219705211's avatar
User1591865219705211
Icon for New Contributor rankNew Contributor
5 years ago
Solved

What the problem is about the circuit?

Hello everyone.

I made a circuit like this.​The Simulation is like this.

The TFF has triggered before the "Toggle" single rise up.

I use Quartus FPGA lite 18.1 and 19.1. The simulation is same.

I tried to program it to fpga dev board(EPM240T100C5N). The situation is also same.

I asked this problem to our school teachers.They also can't solve this problem.

I wanna know why the TFF is triggered to high before Clk and "test" signal at the start time.

So what the circuit problem is? Thank you.

4 Replies

    • User1591865219705211's avatar
      User1591865219705211
      Icon for New Contributor rankNew Contributor
      5 years ago

      I Know the TFF is triggered to high and then it can't not be toggle again.But the TFF is not trigger by CLK or "test" signal.It toggle automatically at the start time.

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        5 years ago

        I'm not sure I understand what you are saying here. As suggested, if you used an OR gate instead of an AND gate, it would work.

        #iwork4intel

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi,

    There is low toggle resulted by AND gate as high input toggle and low q_bar

    Change it to OR gate to make it toggle.

    Thanks,

    Regards