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User1591865219705211
New Contributor
New ContributorWhat the problem is about the circuit?
Hello everyone. I made a circuit like this. The Simulation is like this. The TFF has triggered before the "Toggle" single rise up. I use Quartus FPGA lite 18.1 and 19.1. The simulation ...
Your input to the flip-flop is low because you're ANDing the high Toggle and the low Q_Bar, so the flip-flop doesn't toggle.
https://en.wikipedia.org/wiki/Flip-flop_(electronics)#T_flip-flop
#iwork4intel
SyafieqS
Super Contributor
Super ContributorHi,
There is low toggle resulted by AND gate as high input toggle and low q_bar
Change it to OR gate to make it toggle.
Thanks,
Regards
