Forum Discussion

User1591865219705211's avatar
User1591865219705211
Icon for New Contributor rankNew Contributor
5 years ago
Solved

What the problem is about the circuit?

Hello everyone. I made a circuit like this. ​The Simulation is like this. The TFF has triggered before the "Toggle" single rise up. I use Quartus FPGA lite 18.1 and 19.1. The simulation ...
User1591865219705211's avatar
User1591865219705211
Icon for New Contributor rankNew Contributor
5 years ago

I Know the TFF is triggered to high and then it can't not be toggle again.But the TFF is not trigger by CLK or "test" signal.It toggle automatically at the start time.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

I'm not sure I understand what you are saying here. As suggested, if you used an OR gate instead of an AND gate, it would work.

#iwork4intel