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User1591865219705211
New Contributor
New ContributorWhat the problem is about the circuit?
Hello everyone. I made a circuit like this. The Simulation is like this. The TFF has triggered before the "Toggle" single rise up. I use Quartus FPGA lite 18.1 and 19.1. The simulation ...
Your input to the flip-flop is low because you're ANDing the high Toggle and the low Q_Bar, so the flip-flop doesn't toggle.
https://en.wikipedia.org/wiki/Flip-flop_(electronics)#T_flip-flop
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User1591865219705211New Contributor
New ContributorI Know the TFF is triggered to high and then it can't not be toggle again.But the TFF is not trigger by CLK or "test" signal.It toggle automatically at the start time.
sstrell
Super Contributor
Super ContributorI'm not sure I understand what you are saying here. As suggested, if you used an OR gate instead of an AND gate, it would work.
#iwork4intel
