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Altera_Forum
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12 years ago

What is Timing between nCEO and DCLK in a multi-device AS Configuration ?

Is there timing requirements between nCEO and DCLK when configuring two FPGA's from one EPCS device? The master device (the first FPGA configured) operates in an AS configuration mode and once ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The problem has been resolved. My expensive PCB layout tool was not supposed to let me cross my signals, but some how it did. DATA0 and DCLK on the FPGA that would not configure were swapped on the PCB but not on the schematic. Its over. I can get on with the project and my life again.