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2 Replies
- Altera_Forum
Honored Contributor
The data rate is limited by the core clock, the involved DDR registers and the I/O. I would expect at least 800 Mbps. But without the hardware SERDES DPA functionality, you'll possibly have difficulties to get meaningful data from the serial input, considering delay skew.
- Altera_Forum
Honored Contributor
Hi,
How to implement soft-Serdes in core logic?