New Contributor
Frequent ContributorHi myrfy001,
I believe your question has been addressed through IPS.
Kindly refer to the IPS for the details.
In the R-Tile AVST interface, the Header and Data are separated. Therefore, for TLP that contains data, when the SOP signal is asserted, both the header valid and data valid signals are asserted simultaneously. For TLP that does not contain data, the SOP signal indicates that header valid.
Thanks.
Best Regards,
Ven
New ContributorThanks for your reply.
Infact, I did't pay for any IPS service so I only get the reply from your reply.
From your reply, it said that
for TLP that contains data, when the SOP signal is asserted, both the header valid and data valid signals are asserted simultaneously.
It seems that this behaviour is conflict with the section 4.3.1.1 in the "ug20316 R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide", which said :
This is defined to enable pipelined Header/Prefix and Data transfers to meet the bandwidth target. For example, while transferring the Data for one TLP, the Header and Prefix for the next TLP can also be transferred.
To my understanding, the text above addressed that the (header+payload) can be transmitted before the payload. For example, in the first beat, the header is transfered, and in the second beat, the payload is transfered.
And we can also think it in another way, if both the header valid and data valid signals are asserted simultaneously, why split it into two different signals? why don't keep it the same as the PTile which only have one valid signal for both header and payload?
Thanks.
