Altera_ForumHonored Contributor15 years agowhat is the problem with this program. only a short program! always @ (posedge clk or negedge rst_n or posedge alarm) if(!rst_n || alarm) cnt_s <= 7'b0; else if (cnt_s == 7'd60 ) begin cnt_m <= cnt_m + 1 ; cnt_s <= 7'b0 ; end er...Show More
Altera_ForumHonored Contributor15 years agoyes ... thanks for your answer... i have used it in another always blocks
Recent DiscussionsQuartus Prime Pro 25.1 fatal error during fitter: Windows "Efficiency mode" requiredInquiry regarding purchasing FPGA licensesCyclone 10 LP's Extended Industrial partsAgilex 7 F/I Series True Differential Input TerminationSolvedAgilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When UnpoweredSolved