What is the maximum clock frequency input (CLK0p) for a Max10 single supply voltage(10M02SCU169I7G)?

Yes - you should consider compiling a representative design before completing any hardware. Using Quartus allows you to both confirm pinouts and helps you with timing issues.

You mention input frequency. Modern FPGAs, inclucing MAX 10, have PLLs allowing you to configure the speed at which the logic is clocked. Providing you chose a sensible input frequency for your source clock you will be able to retain a great deal of flexibility through the FPGA design. Failing that it's usually not hard to find a clock source, in the same package, with a different frequency...

Cheers,

Alex