What is the criteria that must be met for the "locked" output in the ALTPLL megafunction to go low?

I am using the ALTPLL IP block with a 30MHz reference clock and Quartus15.1.

From my understanding, the "locked" output of the ALTPLL megafunction will go low as soon as the phase frequency detector of the PLL detects a phase shift between the input reference clock and the feedback clock of the PLL.

There are given a number of reasons why this could happen in the MAX10 Clocking and PLL User Guide:

• Jitter on the reference clock
• Reference clock is not within the defined frequency
• Noise on the power supply
• etc.

Now my questions are:

1. Is it true, that the only reason for the "locked" output to go low is the detection of a phase shift between reference clock and PLL feedback (whatever the reason for that may be)?
2. If so, then how big does that phase-shift need to be in order to force the "locked" output low?

I am using the MAX10: 10M25SCE144