What is the criteria that must be met for the "locked" output in the ALTPLL megafunction to go low?

Thank you for the response,

as I mentioned, I found the list of reasons which may cause the PLL to lose lock. What I do not know, and what I fail to find on the link you referenced, is: How are these "lock loss reasons" evaluated? My understanding so far is, that the only detection for any of the issues listed (Jitter, SSN, PLL reset) , is the detection of a phase difference between reference clock and PLL feedback loop. Is this assumption correct, or are there other means by which the PLL can detect a violation of the PLL specifications?

Thank you and kind regards