What is the best way to minimize I/O skew between pins in timequest

Question

Dear expert,

I would like the max delay from rising edge of clk to FPGA pins to be 1ns for m & n pins. What is the best constraint I can do?

I have these codes:

output reg[7:0] m;

output reg[15:0] n;

always@ (posedge clk)

begin

a<=something;

b<=something;

end

Appreciate much if you could reply asap...

altera_forum · Answer

Look into the "set_output_delay" and "set_max_skew" constraints.

However, obtaining a < 1ns tCO is, I think, not possible. At least for TTL/CMOS

outputs, the tCO is much larger.

What you can do is drive the output registers with a different clock signal, phase shifted from the output clock, using a PLL.

This way, you can get whatever relation you need between the outputs and the output clock signal.

Using the falling edge of the clock signal to drive the output registers, with the correct output delay constraints, may also suit your needs.

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