What is the best way to minimize I/O skew between pins in timequest

Look into the "set_output_delay" and "set_max_skew" constraints.

However, obtaining a < 1ns tCO is, I think, not possible. At least for TTL/CMOS

outputs, the tCO is much larger.

What you can do is drive the output registers with a different clock signal, phase shifted from the output clock, using a PLL.

This way, you can get whatever relation you need between the outputs and the output clock signal.

Using the falling edge of the clock signal to drive the output registers, with the correct output delay constraints, may also suit your needs.