What is the best way to generate multiple clocks with minimum jitter and delays?

Hi,

Thank you for replying. The 1.5GHz and 3GHz outputs from fPLL and zero-delay mode 150MHz output from a cascaded PLL would work for me. However, I think it's not possible to generate a 150MHz clock output using a PLL from 1.5GHz clock. I also checked it: the transceiver PLL's don't supports outputs below 800MHz, while the IOPLL cannot take reference clock frequency more than 700MHz.

Another option is to first generate a clock at 150MHz using IOPLL in zero-delay mode, and then use it as a reference clock to generate 1.5GHz and 3GHz clocks using an fPLL. However, the fPLL does not show the option to source-synchronize the outputs.

Please let me know if you have any suggestions.

Thanks.