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Honored Contributor
Honored ContributorWhat is the best way to generate multiple clocks with minimum jitter and delays?
Hi, I have to generate several clocks on Arria 10 SoC board. The clocks and their applications are as follows: 3GHz clock: for clocking external ADC to sample the incoming data, and receive...
Altera_ForumHonored Contributor
Honored ContributorHey Arvind,
You could use a fPLL to generate the 3GHz clock and 1.5GHz clocks. Then cascade another PLL with this one and generate the 150MHz clock. You could use them in the source-synchronous mode or the Zero-delay mode and have their reset's tied together. Yes, the PLLs in this case may have different locking periods but that can't be avoided. Using one PLL for generating higher frequencies and another for the lower frequencies would be a good option.
