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KK000's avatar
KK000
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7 years ago

What I/O standard shall I use in the pin planner to use a differential pair signal in a FPGA bank connected to 3.3V to compile my project ?

I am connecting VCCIO of some FPGA bank to 3.3 V for interfacing FPGA with ADC and DAC, Can anyone tell me what I/O standard should I give in .QSF for Differential inputs and outputs in Cyclone V F...
KK000's avatar
KK000
Icon for New Contributor rankNew Contributor
7 years ago

Hi,

Actually what I want to know is If I am using I/O standard LVDS for DAC interfaced FPGA bank, does it supply 3.3V or 2.5V to DAC?

Thanks in Advance,