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KK000's avatar
KK000
Icon for New Contributor rankNew Contributor
6 years ago

What I/O standard shall I use in the pin planner to use a differential pair signal in a FPGA bank connected to 3.3V to compile my project ?

I am connecting VCCIO of some FPGA bank to 3.3 V for interfacing FPGA with ADC and DAC, Can anyone tell me what I/O standard should I give in .QSF for Differential inputs and outputs in Cyclone V F...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

For the ADC, the LVDS standard used is 1.8V LVDS, for this the FPGA interface should also match the same LVDS standrad and the IO Bank should be set as 1.8V LVDS.

For the DAC, the LVDS input range is from 800mV to 1600mV, so setting the FPGA interface for the DAC to 1.8V LVDS should work fine for this device too .