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KK000's avatar
KK000
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6 years ago

What I/O standard shall I use in the pin planner to use a differential pair signal in a FPGA bank connected to 3.3V to compile my project ?

I am connecting VCCIO of some FPGA bank to 3.3 V for interfacing FPGA with ADC and DAC, Can anyone tell me what I/O standard should I give in .QSF for Differential inputs and outputs in Cyclone V F...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago
Hello Kabilan, Can you kindly more elaborate on the ADC and DAC transmitter side ? It is also based on the IO frequency performance you would like to use. Also can I know which FPGA device you are using it ? Thank you , Regards, Sree
  • KK000's avatar
    KK000
    Icon for New Contributor rankNew Contributor
    6 years ago

    FPGA device I am using is CycloneV 5CSXFC6F31.

    ADC and DAC used is AD9653 and AD9783 respectively.