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Altera_Forum
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13 years ago

What if design is too big for an FPGA

I was wondering about what to do if a design is too big for an FPGA. Suppose I am trying to make a DSP circuit like the one for H.264 or MPEG video encoding and the FPGA has insufficient resources. Or perhaps I am designing a circuit that has modules that can actually be made separate and implemented on different FPGAs (potentially). What would be the solution to such a problem.

You would say, get a bigger FPGA. What what if we want any other option but this. Are there designs where the circuit is made "multicore" I mean multiFPGA?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Multi FPGA is a possibility. But with good engineering investigation you shouldnt hit the problem as you should have analysed potential resource usage in the first place to make sure it will fit.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    There are different possible solutions to your problem. You have already ruled out one (bigger FPGA).

    Most of the time designs can be re-written to reduce the resource usage (provided you wrote them yourself and are not using IP cores). Quartus will tell you how many resources are used for each design block. Some designs can be reduced more than others.

    Multi-FPGA solutions are always a possibility. (I'm finishing up a project with 7 Cyclone IV FPGAs on the board)
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I am student and just wondering about this point. I am sure people run into this issue and they wonder, oh well lets buy FPGA from some other manufacturer or hmmm lets order an ASIC or hmm wonder what to do now.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    "Ordering an ASIC" is not trivial, and if you're in FPGA developing an ASIC wont be an option. Good design at the front end will help minimise these problems. It will also depend on other limits - some people simply cannot get a larger or more FPGAs, so a redesign may be the only option.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I'm not sure how much information there is out there on partial-reconfiguration or if Altera is supporting it yet, but that could also be a potential solution to the hypothetical issue you proposed, assuming not all of the functions in the design need to be operating concurrently. I suppose this would fall under the category of "resource re-usage".

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    A project manager starts from realistic estimates done by him/her and their team. From that the chip(s) are chosen. This is the crucial point when sales crew from Altera or Xilinx ...etc hoover around right at the premises of their heavy weight customers ready for discount offers and possibly dining out.

    A project may require several chips but I don't know of any tool that will integrate all into a single multichip project(super project) and it doesn't need to. Each chip can have its own project.

    Designs may be migrated to ASIC if they are stable market-wise and there is the thought of lowering cost per unit. But when customers keep asking for new features then FPGAs stay best platform.

    If a single chip is chosen and the design did not fit then the project manager will have to blame the estimates and may resort to the firing squad. But many designs can be reduced by rethinking and personally I believe some 25% is commonly wasted by a moderate designer and up to 70% wasted by beginners. There is unfortunately no tool to measure this wastage.