Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThere are different possible solutions to your problem. You have already ruled out one (bigger FPGA).
Most of the time designs can be re-written to reduce the resource usage (provided you wrote them yourself and are not using IP cores). Quartus will tell you how many resources are used for each design block. Some designs can be reduced more than others. Multi-FPGA solutions are always a possibility. (I'm finishing up a project with 7 Cyclone IV FPGAs on the board)