What are the differences between Altera & Xilinx Deserialization?

With Altera Cyclone family the DESER function is implemented ín logic as well and they have no DPA available. Starting with Cyclone III, PLL dynamic phase shift could be used as a DPA replacement, but I didn't yet need it for similar applications. I assume, that your ADC application has bit rates up to 600 or 700 MBPS, it it could basically work e.g. with Cyclone III and fixed receive phase.

You can get a bit swap issue, if dynamical phase align operation crosses a word boundary. For the said speed range, I prefer to adjust the receiver PLL phase manually to center of the receive window, the PLL is clocked by the ADC FCO.