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Altera_Forum
Honored Contributor
Honored ContributorWeird sticky bit in SPI data
I'm using the Altera SPI Verlog code as a basis for an SPI / SD card interface for a Z80 based computer using a MAX3000A as the CPLD. When I clock the SPI bus at a low data rate (around 430Khz ...
Altera_ForumHonored Contributor
Honored ContributorI sorted the clock divider issue out in the end. Increment the counter on the negative edge of the clock and use the value on the positive edge. I guess I was getting some ripple delay in the counter increment.
It now works perfectly. So ultimately it looks like the sample code isn't fit for use, which is a shame... :(
