Forum Discussion
omar_ibrahim
New Contributor
New Contributorweird behaviour of fitter in quartus for SDRAM project
I've been working on SDRAM controller project using verilog using cyclone v 5cefa5f23i7.
The SDRAM have four bank , 3 cas latency and 166 Mhz clock.
I start design with a goal of having lowest po...
sstrell
Super Contributor
Super ContributorAny reason why you are not using the included EMIF IP instead of trying to reinvent the wheel?
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