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SYadl2's avatar
SYadl2
Icon for New Contributor rankNew Contributor
5 years ago

we have below two questions 1.Can we use fpll in arria10 devices for user logic clock generation. we chose fpll as the normal pll is not supported fractional divider value 2. Mentioned second question below

2. while generating two frequencies(360,156.25) from one pll we are not able to get exact frequency in one of the frequency. do v need to use seperate plls for generating these two frequencies.
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you