Forum Discussion
PGigl
Occasional Contributor
7 years agoWe are getting the following message "Design requires adding a large amount of routing delay".
We are getting the following message "Design requires adding a large amount of routing delay". We have examined the paths with this issue and they are clock crossings. We have put in false paths on t...
KhaiChein_Y_Intel
Regular Contributor
7 years agoHi,
Can you check if this constraint is being ignored in the Timing Analyzer?
Thanks.