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Altera_Forum
Honored Contributor
16 years agoWarnings of uart_receiver to solve
The receiver of UART contains input pins like rxd,clk. and outpu pins like RDR whose value depend on the RXD.Now I got two warnings.1.Warning: Output pins(all) are stuck at VCC or GND,2.Warning: Design contains 5(all) input pin(s) that do not drive logic. As you may know that the output of the design completely depends on the input rxd which I didn't assign. Then I looked into the map viewer only finding there are no connections amount the pins.Help me.
4 Replies
- Altera_Forum
Honored Contributor
your program may stuck at some point that lead to no reset or no evaluate to your signal . you may check your program carefully for logic error.
- Altera_Forum
Honored Contributor
Do you actually intend a FF, that can never be reset, execpt on power-on?
- Altera_Forum
Honored Contributor
I've got the similar warning:
Warning: Reduced register "inst31" with stuck data_in port to stuck value VCC trying to compile a part of y design (Problem.jpg). I've found solution using buffer - carry (Sollution.jpg) - Altera_Forum
Honored Contributor
How to deal with these kinds of warnings??
Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "RDR[0]" is stuck at GND Warning (13410): Pin "RDR[1]" is stuck at GND Warning (13410): Pin "RDR[2]" is stuck at GND Warning (13410): Pin "RDR[3]" is stuck at GND Warning (13410): Pin "RDR[4]" is stuck at GND Warning (13410): Pin "RDR[5]" is stuck at GND Warning (13410): Pin "RDR[6]" is stuck at GND Warning (13410): Pin "RDR[7]" is stuck at GND Warning (13410): Pin "SETRDRF" is stuck at GND Warning (13410): Pin "WRONG" is stuck at GND Warning: Design contains 5 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "bclkX8" Warning (15610): No output dependent on input pin "RDRF" Warning (15610): No output dependent on input pin "sysclk" Warning (15610): No output dependent on input pin "RST_B" Warning (15610): No output dependent on input pin "RxD" Warning: No paths found for timing analysis