Altera_Forum
Honored Contributor
15 years agoWarnings in Quartus
I have a system in which I am attempting to run program code from sdram on a DE2 board. I get the following warnings after quartus compilation.
Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "SDRAM_cke" is stuck at VCC The pin SDRAM_cke is connected directly to the corresponding output from the SOPC system. Also, I am getting these warnings... Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning: Found pins functioning as undefined clocks and/or memory enables Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details When I check the the ignored assignments I see the following: Fast Input Register sdram za_data[0] ON Compiler or HDL Assignment There is an entry for each data bit on the sdram. When I check the ignored timing assignments I see this entry... Cut Timing Path On * data_in_d1 first_nios2_system_reset_clk_0_domain_synch_module No timing path applicable to specified source and destination When I try to run code I get the infamous verify failed message from the memory of my sdram. I have a PLL connected to the sdram clock pin with a -3ns phase shift. I am using the "e" version of the Nios 2 cpu. I have been struggling with this issue for some time. Any help would be appreciated Chase