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Well if this is indeed what I want (not entirely sure because I don't have much experience with using SDRAM) then I did not set it this way explicitly. ALso, the warning came into my system after I added the SDRAM. When I first added the component, this warning was not there. It only came several compilations and changes later.
Thank you for your input. I can't see any direct consequences of any of these warnings.... I am basically looking for the reason why my code always fails when run from SDRAM.... The infamous verify failed message is killing me...
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Hi,
some explanations about the other warnings:
warning: ignoring invalid fast i/o register assignments. see the ignored assignments panel in the fitter compilation report for more information. The assignment should force the Fitter to place the input FF in a FPGA I/O cells. The warning means that the FF could not implement in the I/O cell. Maybe it is worth to
look for the reason.
warning: found pins functioning as undefined clocks and/or memory enables Quartus found some signals which are used as Clock or Enable, but are not expressly defined as such.
cut timing path on * data_in_d1 first_nios2_system_reset_clk_0_domain_synch_module no timing path applicable to specified source and destination This simply means that Quartus could not find a path. Check path name .
Kind regards
GPK
Honored Contributor
