Warning: RST port on the PLL is not properly connected

Hello!

I'm using PLL in my project for the Cyclone V device. And i have this warning in Quartus (Quartus Prime 16.0):

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Warning: RST port on the PLL is not properly connected on instance pll100: pll100_inst|pll100_0002: pll100_inst|altera_pll:altera_pll_i|general[0].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock.

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In PLL IP Core (Name altera_pll, Version 16.0) settings i turn on PLL Auto Reset, but the warning did not disappear.

So, it turns out that in any case i must manually control PLL reset port? Maby there is some guidelines how to do it? I have not found certain recommendations about it.

Sorry for my english...