Warning: RST port on the PLL is not properly connected

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Hi coder, I recommend looking at Alex's suggestion in this thread, it helped me.

http://www.alteraforum.com/forum/showthread.php?t=50680&p=208790#post208790

Basically drive the PLL reset based on the locked output. The recommendation to use a counter is a good idea.

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Thanks for the advice. The idea of Alex's suggestion is clear.

It seems me strange that i turn on PLL Auto Reset (that automatically self-resets the PLL on loss of lock), PLL reconfiguration and clock switchover is not enabled in the design and i still have a warning: "The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock."