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Occasional ContributorWarning: Node: WRN was determined to be a clock but was found without an associated clock assignment.
Hello, I have a input signal WRN (Write enable) driven by microcontroller. I use WRN's rising edge to read the data on the bus. The code fragment is:
IF ( WRN'event AND WRN= '1' ) THEN
datum <= adbus( 15 DOWNTO 0 );
Now, during compilation I get the warning "WRN was determined to be a clock but was found without an associated clock assignment" and the fitter reports "Design is too large" error.
please suggest how should I constrain the WRN signal in the SDC file to avoid the warning for a successful compilation. Thank you!
Update:
I created a rising edge detector signal 'WRN_re'
WRN_re <= (WRN_d XOR WRN) AND WRN; -- WRN_d is the delayed version of WRN (generated from a clocked process)
I used this signal to read data from the bus instead. The warning still exists. After checking the RTL viewer, I clearly see that WRN is never connected to clock pin of any flip flop.
Now I do not understand why the comiler is considering WRN as a clock and throwing the warning.
Also the new error pops up:
Error (332000): Following required options are missing: -clock
---------------------------------------------------------------------------
Usage: set_input_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>
-h | -help: Short help
-long_help: Long help with examples and possible return values
-add_delay: Create additional delay constraint instead of overriding previous constraints
-clock <name>: Clock name
-clock_fall: Specifies that input delay is relative to the falling edge of the clock
-fall: Specifies the falling input delay at the port
-max: Applies value as maximum data arrival time
-min: Applies value as minimum data arrival time
-reference_pin <name>: Specifies a port in the design to which the input delay is relative
-rise: Specifies the rising input delay at the port
-source_latency_included: Specifies that input delay includes added source latency
<delay>: Time value
<targets>: List of input port type objects
---------------------------------------------------------------------------
while executing
"set_input_delay –clock CONTCLK_IN 5 [get_ports WRN]"
The command in bold is the SDC command I have used for WRN. Is the syntax of the SDC command right? I followed the Quartus tutorial to write this command.
Requesting your help. Thank you in advance!
18 Replies
NShan12Update:
I created a rising edge detector signal 'WRN_re'
WRN_re <= (WRN_d XOR WRN) AND WRN; -- WRN_d is the delayed version of WRN (generated from a clocked process)
I used this signal to read data from the bus instead. The warning still exists. After checking the RTL viewer, I clearly see that WRN is never connected to clock pin of any flip flop.
Now I do not understand why the comiler is considering WRN as a clock and throwing the warning.
Also the new error pops up:
Error (332000): Following required options are missing: -clock
---------------------------------------------------------------------------
Usage: set_input_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>
-h | -help: Short help
-long_help: Long help with examples and possible return values
-add_delay: Create additional delay constraint instead of overriding previous constraints
-clock <name>: Clock name
-clock_fall: Specifies that input delay is relative to the falling edge of the clock
-fall: Specifies the falling input delay at the port
-max: Applies value as maximum data arrival time
-min: Applies value as minimum data arrival time
-reference_pin <name>: Specifies a port in the design to which the input delay is relative
-rise: Specifies the rising input delay at the port
-source_latency_included: Specifies that input delay includes added source latency
<delay>: Time value
<targets>: List of input port type objects
---------------------------------------------------------------------------
while executing
"set_input_delay –clock CONTCLK_IN 5 [get_ports WRN]"
The command in bold is the SDC command I have used for WRN. Is the syntax of the SDC command right? I followed the Quartus tutorial to write this command.
Requesting your help. Thank you in advance!
- NShan12
Hello sstrell,
Thank you for your reply.
This is an asynchronous interface between Microcontroller and FPGA. The FPGA waits for WRN's rising edge and then reads the data on bus. Since there is no clock involved, I cannot modify the code as per your suggestion.
Is there any other way you think to solve this?
One hint: I will check if I can proceed with reading data when WRN = '0' instead? This wouldnt confuse the compiler about WRN.
I will look into the fitter error, no need to worry about that now.
sstrellSuper Contributor
You've written this code such that WRN looks like a clock instead of an enable. You should have something like this:
process (clk)
begin
if rising_edge(clk) then
if WRN='1' then
datum <= adbus(15 downto 0);
Then of course you need an SDC constraint for clk. WRN would have a set_input_delay constraint.
As for why you're getting a no fit error, it most likely would not be because of this issue, which is just a warning. Something else is using up resources in your design.
#iwork4intel
