Forum Discussion
Occasional ContributorWarning: Node: WRN was determined to be a clock but was found without an associated clock assignment.
Update:
I created a rising edge detector signal 'WRN_re'
WRN_re <= (WRN_d XOR WRN) AND WRN; -- WRN_d is the delayed version of WRN (generated from a clocked process)
I used this signal to read data from the bus instead. The warning still exists. After checking the RTL viewer, I clearly see that WRN is never connected to clock pin of any flip flop.
Now I do not understand why the comiler is considering WRN as a clock and throwing the warning.
Also the new error pops up:
Error (332000): Following required options are missing: -clock
---------------------------------------------------------------------------
Usage: set_input_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>
-h | -help: Short help
-long_help: Long help with examples and possible return values
-add_delay: Create additional delay constraint instead of overriding previous constraints
-clock <name>: Clock name
-clock_fall: Specifies that input delay is relative to the falling edge of the clock
-fall: Specifies the falling input delay at the port
-max: Applies value as maximum data arrival time
-min: Applies value as minimum data arrival time
-reference_pin <name>: Specifies a port in the design to which the input delay is relative
-rise: Specifies the rising input delay at the port
-source_latency_included: Specifies that input delay includes added source latency
<delay>: Time value
<targets>: List of input port type objects
---------------------------------------------------------------------------
while executing
"set_input_delay –clock CONTCLK_IN 5 [get_ports WRN]"
The command in bold is the SDC command I have used for WRN. Is the syntax of the SDC command right? I followed the Quartus tutorial to write this command.
Requesting your help. Thank you in advance!
Super ContributorHi,
Just to make some corrections:
You need false paths or set_input[output]_delay on all I/O to fully constrain the design. - Yes, I will make sure this is do
You cannot simple false path the input delay. As this need to be analyze. You can set input delay on it. Analyze those path in timing analyzer to see if you can close those timing.
Set input delay had to be associated with a clock. You need to understand where does those port connected to the external device. Those port must have associated with a clock inside the fpga or outside the fpga(virtual clock)
You need to create a generated clock constraint on the output port.
To explain this, this is used usually if you have a PLL/any clock that is connected to the output port. This usually will be use together with your set-input-delay or output-delay. Depending on your design on how you would like to associate the clock with it.
Occasional ContributorHello kTan_Intel,
I have used both set_input_delay and set_false_path command after analyzing the input paths from the Bus interface and ADC to the FPGA.
Regarding the generated clocks, In case of DAC interface, clock to DAC is derived from main clock and is connected to output port.
In ADC interface: I have a pulse signal triggered in a state machine that sends sample command to ADC (to sample data at 2MHz). This can be considered clock, but I am not sure if it actually is a clock. Can I use similar generated clock command for the pulse signal too
