Forum Discussion
Altera_Forum
Honored Contributor
17 years agoWarning: Can't achieve minimum setup and hold requirement Clk along 11 path(s)?
could you please tell me as to what it means and how to get rid of it? I have a grey code counter connected to D flip flops through some combinational logic in the path. in the report it say...
Altera_Forum
Honored Contributor
17 years agoNot enough info. Are you using Classic Timing Analyzer? Right-click on one of these and do a Locate Path. It will give details below. You need to figure out if:
a) The requirement is correct. (For example, a transfer within a 10ns clock domain usually has a 10ns setup requirement and a 0ns hold requirement) b) Is there significant clock skew causing it to fail timing. This is usually a result of gated clocks, and if bad enough, creates requirements that can't meet timing regardless of the datapath. c) If this is all correct, then it's something in your datapath. Is it too many levels of logic? Is it placed badly? Etc. (Those apply more to setup violations, which are the more common one.)