virtual clock - latch and launch clock on same cycle

Hi Nitzan,

It seems like you are encountering a setup timing violation issue in your design involving a virtual clock in a .fdc It is hard to see without the full constraint. I am suspecting there might be an issue on the input/output delay calculation that causing the launch and latch clock to be in the same phase.

Also another question - do the real clock and virtual clock should be in the same async group?

-From what I am seeing, in the scenario you've described with a real clock and a virtual clock, the concept of asynchronous clock domains might not directly apply. Both clocks are likely derived from the same master clock and are intended to be related, just with different clock frequencies or phases. Therefore, they may not need to be considered as separate asynchronous clock domains