Virtex-6 XC6VLX195T device

The Stratix IV series would be similar. Take a look in the Stratix IV and Stratix V handbooks at their tables of device features, and do the same for the Virtex device.

What are you looking to use the Altera device for? If you list some of the I/O requirements and internal logic requirements, you can get some more feedback. For example, perhaps a lower-cost Arria or Cyclone could be used for your design.

Cheers,

Dave

Hi, Dave. Thanks.

Xilinx device I mentioned has:

Number of Slice Registers (max 249600)

Number of Slice LUTs (max 124800)

Number of fully used LUT-FF pairs (max 969)

Number of bonded IOBs (max600)

Number of Block RAM (max: 344)Number of GCLKs (max 32)

I found several devices in Startix IV, for example

Startix IV EP4SGX290FF35C2X

Registers 232960

Pins 644

My I/O requirements are max pins needed 549.

Startix V has bigger number of registers (starts with 300k) the only device that has cose to 200k registers has inadequate pin count.

thanks,

mj

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My I/O requirements are max pins needed 549.

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If you look at Table 1-1 in the Stratix IV handbook, there are several GX devices with in excess of 549 user I/Os. Table 1-4 shows there are also several E series devices with enough pins too.

The GX devices have high-speed transceivers, as do the more expensive GT devices. If you do not need the transceivers, then look at the E series resources to see if they meet your needs.

Cheers,

Dave

Hi Dave,

Thanks for your help so far. Do Altera devices have BRAM? Or I need to have certain settings in order to unable it?

Thanks,

mj

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Thanks for your help so far. Do Altera devices have BRAM? Or I need to have certain settings in order to unable it?

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Yes, the devices have distributed RAM equivalent to Xilinx BRAM. Each device has blocks of RAM of various sizes. The names of the RAM changes depending on the whims of Altera marketing. For example, the Stratix IV handbook indicates those devices have 'tri-matrix' memory blocks consisting of M9K (9216-bits), M144K 147456-bits), and MLAB (640-bits) memory blocks.

These blocks can be used for memory, dual-port FIFOs, etc., pretty much all the same stuff as BRAMs can be used for.

The Quartus II handbook has details on how you can infer these memory blocks from VHDL or Verilog, or you can use the MegaWizard manager to instantiate a specific component. I typically use the MegaWizard to get an example instantiation of the component, and then use the altsyncram or whatever component it instantiates directly in my code.

Cheers,

Dave

Hi Dave,

I have 2 vhdl files each containing the definition for one of the lookup tables used in the CRC calculation. On one hand I have 256x32-bit single-port distributed Read Only RAM (LUT) and on hte other hand 256x32-bit single-port distributed Read Only RAM - BRAM based. I need to configure BRAM vhdl file in order to use memory blocks you mentioned.

I tried using MegaWizard but I couldnt locate altsyncram megafunction. Could you be able to give me an example on how to do this?

Thanks,

mj

Hi MJ,

So basically you need:

* 256x32-bit single-port ROM

* 256x32-bit single-port RAM

Lets say you have a project with a Stratix IV GX device selected as the target device. Select Tools->MegaWizard Plugin Manager, then new variation, then expand the memory compiler folder. Under that you will see RAM: 1-port and ROM: 1-port. Lets start with the RAM since you do not need to initialize it; select 1-port RAM, select VHDL as output, name it ram0.vhd, and then configure the size as 32 x 256. Leave the rest at their defaults. Later you can read the pages and see if you want to add features. Click finish.

Now open up the ram0.vhd file. Inside this file you will see that the MegaWizard has instantiated an altsyncram component. This component is defined in the altera_mf VHDL library. You can instantiate it directly, rather than using the MegaWizard. Since I like to control the generics on the ports, I use the MegaWizard to give me a template (an example configuration), and then I throw that code away. You may prefer to use the ram0.vhd file directly. I just wanted to help show you how the tool operated.

The ROM can be instantiated in a similar manner, except that you will need to provide an initialization file for the ROM contents. Its called a .mif file. I'm not sure of the format. The Altera documents will have details.

Cheers,

Dave

Thanks a lot!

Cheers,

Mary

Hello Dave,

is it possible to contact you on your email address? I have some more questions in regards to previous topic.

regards,

mj

Hi MJ,

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is it possible to contact you on your email address? I have some more questions in regards to previous topic.

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Sure.

Cheers,

Dave