Virtex-6 XC6VLX195T device

Hi MJ,

So basically you need:

* 256x32-bit single-port ROM

* 256x32-bit single-port RAM

Lets say you have a project with a Stratix IV GX device selected as the target device. Select Tools->MegaWizard Plugin Manager, then new variation, then expand the memory compiler folder. Under that you will see RAM: 1-port and ROM: 1-port. Lets start with the RAM since you do not need to initialize it; select 1-port RAM, select VHDL as output, name it ram0.vhd, and then configure the size as 32 x 256. Leave the rest at their defaults. Later you can read the pages and see if you want to add features. Click finish.

Now open up the ram0.vhd file. Inside this file you will see that the MegaWizard has instantiated an altsyncram component. This component is defined in the altera_mf VHDL library. You can instantiate it directly, rather than using the MegaWizard. Since I like to control the generics on the ports, I use the MegaWizard to give me a template (an example configuration), and then I throw that code away. You may prefer to use the ram0.vhd file directly. I just wanted to help show you how the tool operated.

The ROM can be instantiated in a similar manner, except that you will need to provide an initialization file for the ROM contents. Its called a .mif file. I'm not sure of the format. The Altera documents will have details.

Cheers,

Dave