Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

View internal signals when simulating testbech (.vht) in ModelSim-ALTERA

After writing and compiling my .vhd program, I create a testbench in Quartus II (Processing > Start > Start Test Bench Template Writer). This process creates a .vht file. After editing and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

When probing the synthesized design using SignalTap II, you can use synthesis attributes; keep, preserve, and noprune to stop synthesis from eliminating signal names. I've never tried this with the simulator, but it likely preserves them there too.

Cheers,

Dave