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Altera_Forum
Honored Contributor
Honored Contributorvideo glitches when activate commands
hi, i develop one video system using custom ip and altera VIP suite components.
Essentially i display a frame buffer or my video elaboration. The video input is the same for the frame buffer and my logic, i use a CPR to replicate it. my logic starts when i write '1' in a register of my custom component. I see that when i enable my logic the video image is flickering a bit, and i see some green.... this noise is not always the same, some time it occupies the whole frame, some others only a little piece this happens even if the frame buffer image is displayed ( and my logic runs in background) maybe i have too much masters connected with the memory controller? i stall the video input only for short periods of time while i'm writing data in memory2 Replies
Altera_ForumCheck the priorities of each Avalon master's accesses to the memory containing the frame buffer.
You need the display code to be the highest priority. You may also need to control the number of cycles each master does before relinquishing the slave. If the display needs a more memory bandwidth that it gets when its accesses are interleaved with those from the writing master you'll need to artificially reduce the write cycles so that the display hardware can do two back-to-back bursts. I had 'fun' a few years back getting a SA1100/SA1101 system to display data on an LCD panel because slow cpu cycles (eg pcmcia) interleaved with display reads caused the display to underrun. The 'fix' was to lower the pixel clock during such accesses!- Altera_Forum
i tried to change the arbitration shares with no results.
i also tried to improve the burst lenght of my memory reader and this worked! there is a way to do it in sopc builder?
