video glitches when activate commands

Check the priorities of each Avalon master's accesses to the memory containing the frame buffer.

You need the display code to be the highest priority.

You may also need to control the number of cycles each master does before relinquishing the slave.

If the display needs a more memory bandwidth that it gets when its accesses are interleaved with those from the writing master you'll need to artificially reduce the write cycles so that the display hardware can do two back-to-back bursts.

I had 'fun' a few years back getting a SA1100/SA1101 system to display data on an LCD panel because slow cpu cycles (eg pcmcia) interleaved with display reads caused the display to underrun. The 'fix' was to lower the pixel clock during such accesses!