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Rhydian's avatar
Rhydian
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31 days ago
Solved

Video generation with altlvds_tx and external PLL

Hi, We have a design targeting a Cyclone IV E with LVDS video output for an LCD panel. There are several different variants of HDL code with different hard-coded display resolutions, but the one I ...
Programmable Logic Device
  • Rhydian's avatar
    Rhydian
    30 days ago

    I fixed it.

    It was a case of RTFM - the 'slow' clock input to the atltlvds_tx block needs to be half the pixel clock frequency, I found this buried in the timing reports from the old design.  Once I reconfigured the PLL again to give a third output at 36 MHz, it all works perfectly and passes timing.

    This info is also in an information panel in the MegaWizard GUI, I didn't see it the first time.  

Rhydian's avatar
Rhydian
Icon for New Contributor rankNew Contributor
30 days ago

I fixed it.

It was a case of RTFM - the 'slow' clock input to the atltlvds_tx block needs to be half the pixel clock frequency, I found this buried in the timing reports from the old design.  Once I reconfigured the PLL again to give a third output at 36 MHz, it all works perfectly and passes timing.

This info is also in an information panel in the MegaWizard GUI, I didn't see it the first time.