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Altera_Forum
Honored Contributor
Honored ContributorVHDL/Modelsim bug?
Hello, i have two modules sending signal to each other, one module has the following code when WAIT_REQ_DATA =>
-- Wait for a requisition from the Goertzel module
if req_data = '...
Altera_ForumHonored Contributor
Honored ContributorAs such it is perplexing without knowing fullm picture. However I note the change occurs when get_sample gows low. Do you have any conditions apart from if somewhere up the process
