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Altera_Forum's avatar
Altera_Forum
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14 years ago

VHDL/Modelsim bug?

Hello, i have two modules sending signal to each other, one module has the following code when WAIT_REQ_DATA => -- Wait for a requisition from the Goertzel module if req_data = '...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Both modules are recieving the same clock input (50 mhz) directly from the pin.

Data_ready_in is an input that is connected in the get_data_reg_next from my second module 


when INCREMENT =>
        -- Increment signals for processing
        data_output_reg_next   <= acc_reg;
        data_ready_reg_next    <= '1';

and it goes to zero one state after..