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Altera_Forum's avatar
Altera_Forum
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14 years ago

VHDL/Modelsim bug?

Hello, i have two modules sending signal to each other, one module has the following code when WAIT_REQ_DATA => -- Wait for a requisition from the Goertzel module if req_data = '...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

how do you generate data_ready_in.

if it is not generated on same clock you might get problems of delta delay or actual delay that is not visible in waveforms