Vhdl?

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Thanks Mixa :)

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No problem :) just a click on "Add to cms's Reputation" link at the top rigth of the post.

Normally, I would refuse to edit such confuse VHDL code. It should be noted, that A_REP isn't a standard VHDL library function, I see that it's defined in altera_europa_support_lib.vhd. It's not clear to me, if it works at all to apply A_REP to the boolean result of a relational operation.

It would be much better to use understandable standard VHDL

if address = "00" then
read_mux_out <= data_out;
else 
read_mux_out <= (others => '0');
endif;

respectively an conditional assignment in concurrent code.

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Hi gicolleta,

the statement works right but too complicated to such simplest task :)

1. std_logic_vector'("000000000 000000000000000000000") & (address) - produce 32bit vector from 2-bit address?

2. compare it with 32'h0 and get one-bit result: to_std_logic((((std_logic_vector'("000000000 000000000000000000000") & (address)) = std_logic_vector'("0000000000000000000000000000000 0")))

3. replicate result upto data_out length vector : REP_A(0/1, 13)

4. Finally just bit-wise AND data_out with '0 or '1 vector - propagate data_out to mux or not.

Alternative:

read_mux_out <= (others => '0') when address = "00" else data_out;

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Thanks Mixa :)

Hi gicolleta,

the statement works right but too complicated to such simplest task :)

1. std_logic_vector'("000000000 000000000000000000000") & (address) - produce 32bit vector from 2-bit address?

2. compare it with 32'h0 and get one-bit result: to_std_logic((((std_logic_vector'("000000000 000000000000000000000") & (address)) = std_logic_vector'("0000000000000000000000000000000 0")))

3. replicate result upto data_out length vector : REP_A(0/1, 13)

4. Finally just bit-wise AND data_out with '0 or '1 vector - propagate data_out to mux or not.

Alternative:

read_mux_out <= (others => '0') when address = "00" else data_out;