Forum Discussion
Altera_Forum
Honored Contributor
17 years agoVhdl?
Can anyone help with explaining how the statement below works? I'm confused as to why you AND data_out? Is the statement saying if address = x then read_mux_out <= data_out S...
Altera_Forum
Honored Contributor
17 years agoI suspect this is one reason why some people unfairly regard VHDL as "verbose" - people write bad code and then call the lanbguage verbose because they don't use the strengths of the language to write simple clear code like the right honourable cms has just demonstrated.