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Altera_Forum's avatar
Altera_Forum
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17 years ago

Vhdl?

Can anyone help with explaining how the statement below works? I'm confused as to why you AND data_out? Is the statement saying if address = x then read_mux_out <= data_out S...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Normally, I would refuse to edit such confuse VHDL code. It should be noted, that A_REP isn't a standard VHDL library function, I see that it's defined in altera_europa_support_lib.vhd. It's not clear to me, if it works at all to apply A_REP to the boolean result of a relational operation.

It would be much better to use understandable standard VHDL 

if address = "00" then
read_mux_out <= data_out;
else 
read_mux_out <= (others => '0');
endif;

respectively an conditional assignment in concurrent code.