--- Quote Start ---
You can set a 'Safe State Machine' in the Analysis & Synthesis Advanced settings. This does about what you want? It detects an illegal state and then transitions to the reset state, but without telling anybody :)
--- Quote End ---
In theory this would be a nice feature, but since you cannot control other registers and especially not output signals, it’s worthless and most likely makes things worse than better. What you need es explicit control over what should happen in such a case.
But, again, you cannot detect inconsistencies beyond this single signal, so if something in the same architecture or even in another entity is expected to run synchronized to your state machine, this will still be out of sync and you need a very high level of redundancy and state monitoring to properly detect reset conditions.
Additionally, such monitoring of unexpected inconsistencies can be combatted by the optimizer which might see opportunities for register collapsing if redundant or similar state machines are not properly constrained.
– Matthias
Honored Contributor
