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Altera_Forum
Honored Contributor
Honored ContributorVHDL works only with xilinx
Hi, I wrote a vhdl code that interface with a module through SPI communication protocol my code was done in FSM with next state logic, it worked perfectly with my spartan 3AN board but when i ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- There is no notion of: Any unencoded state the implemented registers might take. I would call this a ‘when unencoded_state =>’ – a feature of VHDL still to be specified. --- Quote End --- You can set a 'Safe State Machine' in the Analysis & Synthesis Advanced settings. This does about what you want? It detects an illegal state and then transitions to the reset state, but without telling anybody :) --- Quote Start --- Remember: Superfluous warnings are *bad*. --- Quote End --- I hope that stepmother Altera reads this, its IP spits out loads of them ... --- Quote Start --- The answer to this problem space is, again, coding style, and I would strongly recommend reading (and adhering to) this. --- Quote End --- Unfortunately this link is not working.
