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There is no notion of: Any unencoded state the implemented registers might take. I would call this a ‘when unencoded_state =>’ – a feature of VHDL still to be specified.
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You can set a 'Safe State Machine' in the Analysis & Synthesis Advanced settings. This does about what you want? It detects an illegal state and then transitions to the reset state, but without telling anybody :)
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Remember: Superfluous warnings are *bad*.
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I hope that stepmother Altera reads this, its IP spits out loads of them ...
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The answer to this problem space is, again, coding style, and I would strongly recommend reading (and adhering to) this.
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Unfortunately
this link is not working.
Honored Contributor
