VHDL works only with xilinx

'when others=>' should be used since you normally don't control how the enumerated state variable is encoded in hardware. Most synthesizers, by default, will use the one-hot encoding and therefore you will end up with many undefined states. Therefore 'when others=>' is needed. Atleast it should be your practice as a good habit. This prevent any possible hangups in an undefined state.

As far as the reset goes. On most circuits you don't really need a reset since the initial state will be clocked through in a few clock cycles and you get to a known state. However, in a state machine you need to explicitly tell the state machine where to start and not rely on the specific tool to implement it the way it wants to. Otherwise it is a setup for having different simulation/synthesis result.

Not including signals in the sensitivity list will result in latches which in most cases are undesirable