VHDL std_logic_vector Comparisons

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Sure - you can even have record types on the entity.

One problem with integers could mask initialization problems when comparing gate-level simulations with RTL: there is no "X" value for integers. So I try to stick to slv.

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True, but if you are not too concerned with gate level simulation, there is no worry.

Use any type you want for any ports, but at the top level, use a bit-array type, or record of bit array types so you can map each bit to individual pins.